Low k film application for interlevel dielectric and method of cleaning etched features

ABSTRACT

Methods of selectively removing post-etch polymer material and dielectric antireflective coatings (DARC) without substantially etching an underlying carbon-doped low k dielectric layer, and compositions for the selective removal of a DARC layer and post-etch polymer material are provided. A composition comprising trimethylammonium fluoride is used to selectively etch a dielectric antireflective coating layer overlying a low k dielectric layer at an etch rate of the antireflective coating layer to the low k dielectric layer that is greater than the etch rate of the antireflective coating to a TEOS layer. The method and composition are useful, for example, in the formation of high aspect ratio openings in low k (carbon doped) silicon oxide dielectric layers and maintaining the integrity of the dimensions of the formed openings during a cleaning step to remove a post-etch polymer and antireflective coating.

FIELD OF THE INVENTION

[0001] The present invention relates generally to semiconductor devicefabrication, and more particularly to methods of removing post-etchpolymer and dielectric antireflective coatings without substantiallyetching the underlying dielectric layer, and solutions used in suchmethods.

BACKGROUND OF THE INVENTION

[0002] The continuing trend in the semiconductor industry towarddensification of circuit devices has significantly improved performanceof electronic devices that use integrated circuits. In a typicalintegrated circuit, individual circuit elements are electricallyconnected together by a metallization process in which layers of metalare deposited and patterned to form metal lines that complete thecircuit as designed. Multiple metal layers are often employed. Metallines within patterned metal layers are insulated by interleveldielectric layers from undesired electrical contact both with othermetal lines, whether in the same or another metal layer, and with othercircuit elements.

[0003] In the construction of integrated circuit structures, dielectricmaterials such as silicon oxide (SiO₂) have been conventionally used toelectrically separate conductive elements of the integrated circuitstructure. The increasing density of integrated circuits has resulted inunneeded capacitance between metal lines in an integrated circuit whichslows circuit speed and can cause cross-coupling between adjacentconductive elements.

[0004] The use of insulation materials having lower dielectric constants(k values) than conventional silicon oxide (SiO₂) have been described.One such class of material is a carbon doped silicon oxide materialwherein at least a portion of the oxygen atoms bonded to the siliconatoms are replaced by one or more organic groups, for example, an alkylgroup such as a methyl (CH₃) group. Such low k carbon doped siliconoxide dielectric materials have dielectric constants varying from about2.5 to about 3.5, and lowers the capacitance between conductive elementsseparated by such dielectric materials.

[0005] In connecting overlying layers of metal lines separated by acarbon-doped SiO₂ interlayer dielectric (ILD) layer, a photolithographictechnique is used that typically employs a dielectric antireflectivecoating (DARC) layer and an overlying photoresist layer. High aspectratio features such as vias/trenches that are etched through the ILDlayer to an underlying metal line are subsequently cleaned to removepost-etch polymer and the DARC layer before depositing the metal fill.Current cleaning compositions etch a portion of the ILD layer during thecleaning step, which can have a negative impact on and significantlyalter the critical dimensions of the etched feature.

[0006] Therefore, a need exists for a cleaning composition and processthat overcomes such problems.

SUMMARY OF THE INVENTION

[0007] The present invention provides methods of selectively removingdielectric antireflective coatings (DARC) without substantially etchingthe underlying dielectric layer, for example, in the formation ofconductive contacts in a semiconductor structure. The invention furtherprovides compositions for the selective removal of post-etch polymer anda DARC layer. The method and composition help prevent degradation of theexposed surfaces of a low k carbon doped silicon oxide dielectricmaterial during removal of post-etch polymer and antireflective coatingafter formation of vias or contact openings in the dielectric material.

[0008] In one aspect, the invention provides a method of cleaning awafer surface. In one embodiment, the method comprises contacting awafer substrate having overlying layers of a carbon-doped low kdielectric layer, a dielectric antireflective coating layer, andpost-etch polymer material, with a cleaning solution to selectivelyremove the antireflective coating layer and the post-etch polymer, withsubstantially no etching of the low k dielectric layer. Preferably, theetch rate ratio of the DARC layer to the low k dielectric layer isgreater than 5:1, preferably greater than 10:1. In one embodiment, thecleaning composition comprises an effective amount of trimethylammoniumfluoride (TMAF) to selective etch the DARC layer and post-etch polymermaterial. In another embodiment, the composition comprises effectiveamounts of TMAF and hydrogen fluoride (HF). In a further embodiment,effective amounts of TMAF and trimethylammonium hydroxide (TMAH) arecombined to form the cleaning composition.

[0009] In another aspect, the invention provides a method of forming aconductive plug (via plug) and/or interconnect or contact. In oneembodiment, the method includes providing a wafer comprising a substratewith an active area such as a metal line and overlying layers of low kdielectric layer, a dielectric antireflective coating (DARC) layer, anda photoresist layer; forming a opening through the low k dielectriclayer to the active area on the substrate; and contacting the wafer witha cleaning solution to selectively remove the dielectric antireflectivecoating layer and post-etch polymer material with substantially noetching of the low k dielectric layer. A conductive metal can then bedeposited to fill the opening (and/or trench) to form a conductive plugand a metal line (interconnect, contact). The method can be used to formsingle or dual damascene interconnects and via plugs in the manufactureof integrated circuits.

[0010] In yet another aspect, the invention provides a cleaningcomposition comprising one or more cleaning agents in amounts effectiveto selectively remove a dielectric antireflective coating (DARC) layeroverlying a carbon-doped low k dielectric layer at an etch rate of theDARC layer to the low k dielectric layer that is greater than the etchrate ratio of the DARC material to TEOS. In one embodiment, the cleaningcomposition is formulated such that contact of the cleaning compositionwith a carbon-doped low k dielectric blanket layer for a time period ofup to about 15 minutes results in no measurable removal of acarbon-doped low k dielectric layer. In other embodiments, the cleaningcomposition comprises about 10 to about 40 wt % TMAF and, optionally,about 0 to about 10 wt % HF, or about 0 to about 25 wt % TMAH. Thecleaning composition can have a pH over a range of about 3.5 to about14.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Preferred embodiments of the invention are described below withreference to the following accompanying drawings, which are forillustrative purposes only. Throughout the following views, thereference numerals will be used in the drawings, and the same referencenumerals will be used throughout the several views and in thedescription to indicate same or like parts.

[0012]FIG. 1 is a diagrammatic cross-sectional view of a semiconductorwafer fragment at a preliminary step of a processing sequence.

[0013] FIGS. 2-6 are views of the wafer fragment of FIG. 1 at subsequentand sequential processing steps, showing fabrication of a via plug andmetal line according to an embodiment of the method of the invention.

[0014] FIGS. 7-10 depict another embodiment of the method of theinvention in the formation of a via plug, showing steps in thesubsequent and sequential processing of the wafer fragment of FIGS. 1-2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The invention will be described generally with reference to thedrawings for the purpose of illustrating the present preferredembodiments only and not for purposes of limiting the same. The figuresillustrate processing steps for use in the fabrication of semiconductordevices in accordance with the present invention. It should be readilyapparent that the processing steps are only a portion of the entirefabrication process.

[0016] In the current application, the terms “semiconductive waferfragment” or “wafer fragment” or “wafer” will be understood to mean anyconstruction comprising semiconductor material, including but notlimited to bulk semiconductive materials such as a semiconductor wafer(either alone or in assemblies comprising other materials thereon), andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term “substrate” refers to any supportingstructure including, but not limited to, the semiconductive waferfragments or wafers described above.

[0017] An embodiment of a method of the present invention is describedwith reference to FIGS. 1-6. As shown, a dual damascene process is usedto form a via and interconnect associated with an active area of asemiconductor circuit. It is understood that the method of the inventioncan be used in a single damascene process or other process to form a viaplug or metal line.

[0018] The via plug/metal line is illustrated and will be described asbeing coupled to a conductive area 16, but can be used wherever requiredwithin the structure of a semiconductor circuit.

[0019] Referring to FIG. 1, a wafer fragment 10 is shown at apreliminary processing step. The wafer fragment 10 in progress cancomprise a semiconductor wafer substrate or the wafer along with variousprocess layers formed thereon, including one or more semiconductorlayers or other formations, and active or operable portions ofsemiconductor devices.

[0020] The wafer fragment 10 is shown as comprising a substrate 12, aconductive (active) area 14, an overlying interlayer dielectric (ILD)layer 16, and an overlying dielectric antireflective coating (DARC)layer 18. An exemplary substrate 12 is monocrystalline silicon. Theconductive area 14 can comprise a conductor or semiconductor material,for example, a doped silicon region such as a source/drain region, or anunderlying conductive runner or wiring layer, as shown in theillustrated example. The wiring layer can comprise, for example copperor aluminum, or other conductive metal depending upon the function anddesired conductivity of the circuit element.

[0021] The interlayer dielectric (ILD) layer 16 comprises a low k oxidematerial formed over the conductive area 14, typically to a thickness ofabout 2,000 to about 10,000 angstroms. The ILD layer 16 comprises amodified silicon oxide (SiO₂) insulation layer that can be formed usinga carbon-substituted silane precursor such as trimethylsilane (TMS). TheILD layer 16 preferably has a dielectric constant of about 2.5 to about3.5.

[0022] An exemplary process for forming a carbon doped low k siliconoxide ILD layer 16 comprises flowing into a chemical vapor deposition(CVD) chamber, about 60 to about 1000 sccm TMS, with an oxygen sourcesuch N₂O at about 200 to about 1000 sccm, or O₂ at about 50 to about 500sccm, combined with helium (He) to dilute the gases at a flow rate ofabout 200 to about 1,000 sccm or higher, preferably with plasmaenhancement. In an example and preferred process, about 60 to about 150sccm TMS, about 300 to about 500 sccm N₂O, and about 300 to 500 sccm Heare flowed into the deposition chamber. In another example and preferredprocess, about 500 to about 700 sccm TMS with about 80 to about 150 sccmO₂ are flowed into the reaction chamber. A standard CVD chamber can beused, such as a DxZ chamber (Applied Materials). Preferred processingconditions include a temperature of about 300° C. to about 450° C., apressure of about 3 Torr to about 7 Torr, and an rf power of about 200 Wto about 800 W.

[0023] The dielectric antireflective coating (DARC) layer 18 isdeposited over the low k carbon doped ILD layer 16 to a thickness toprovide anti-reflective properties, typically about 150 to about 650angstroms or more. In a photolithography process, the DARC layer 18 aidsin preventing undesirable light reflection during a step of “setting” aphotoresist layer, and also prevents profile distortion. Preferably, theDARC layer 18 reduces reflected radiation reaching an overlying layer ofphotoresist to less than about 10% or as low as less than 1%, dependingon the process sensitivity of incident radiation at the DARC layer 18.

[0024] A variety of DARC materials can be used that absorb variouswavelengths of radiation. Preferably, the DARC layer comprises asilicon-rich oxide or a silicon-rich oxynitride. The DARC layer 18preferably comprises amounts of silicon, oxygen, and nitrogen,optionally with an amount of hydrogen, to form a silicon-rich oxynitridefilm of Si_(x)O_(y)N_(z):H, preferably where x=0.30 to 0.65, y=0.02 to0.56, and z is 0.05 to 0.33, or a silicon-rich oxide Si_(x)O_(y):H,preferably where x=0.30 to 0.65, and y=0.25 to 0.60. The relative valuesof x, y and z and the hydrogen content can be adjusted to alterabsorbence characteristics of the deposited layer. Exemplary DARC filmsinclude silicon, oxygen and nitrogen DARC materials disclosed, forexample, in U.S. Pat. No. 6,225,671 (Yin), U.S. Pat. No. 6,268,282(Sandhu et al.), and U.S. Pat. No. 5,698,352 (Ogawa et al.).

[0025] The DARC layer 18 can be deposited by known processes, such asCVD or preferably by plasma-enhanced CVD (PECVD) including, for example,electron cyclotron resonance (ECR) PECVD, and bias ECR PECVD processes.Exemplary conditions for depositing the DARC layer 18 include flowing asilicon-containing precursor such as silane (SiH₄) at a rate of about 40to about 300 sccm, preferably about 60 to about 225 sccm, preferablyabout 80 sccm; an oxygen source gas such as nitrous oxide (N₂O) oroxygen (O₂) at a rate of about 80 to about 600 sccm, preferably about 95to about 550 sccm, preferably about 80 sccm; with argon, helium or otherinert gas at a rate of about 1300 to about 2500 sccm, preferably about2200 sccm, depending on the photo requirements of the DARC film. Thegases can be flowed into a plasma-enhanced CVD chamber at a temperatureof about 400° C., under a pressure of about 4 Torr to about 6.5 Torr,and an rf power to the chamber of about 50 to about 200 watts,preferably about 100 watts.

[0026] As shown in FIG. 2, a photoresist layer 20 is formed over theDARC layer 18 by known techniques, for example, a spin-on process. Thephotoresist layer 20 can comprise either a positive or negativephotoresist. Exemplary photoresists comprise an organic polymericmaterial, and include those comprising a novolac resin, adiazonaphthaquinone, and a solvent (e.g., n-butyl alcohol or xylene),and negative photoresist materials such as those comprising a cyclizedsynthetic rubber resin, bis-arylazide, and an aromatic solvent.

[0027] As shown in FIG. 3, the ILD layer 16 and the DARC layer 18 canthen be patterned and etched using a known two-tier etch process,typical when forming damascene contacts, to form dual inlaid openingsthat include a contact opening or via 22 and an interconnect channel ortrench 24. Etching of the ILD and DARC layers can be performed usingknown techniques, for example, a plasma etch using one or more of Cl₂,HBr, CF₄, CH₂F₂, and helium and NF₃. Typically, a trench or groove 24 isetched into the ILD layer 16, and then the contact opening 22 is etchedto extend to the underlying conductive (active) region 14 in thesubstrate. The trench 24 forms a channel from the contact opening 22 toother circuit elements (not shown). Typically, the contact opening 22has a width less than about 0.25 μm, more preferably less than about0.20 μm, resulting in an aspect ratio greater than about 0.5, preferablygreater than about 8. The photoresist is removed through an oxygenplasma ashing step, a wet piranha (H₂SO₄/H₂O₂ mixture) step, or acombination of both.

[0028] Referring to FIG. 4, once the etch step and photoresist stripstep are completed, a post-etch cleaning (arrows 26) is performed usinga single step wet etch to selectively remove the DARC layer 18 and anyremaining post-etch polymer 26. Post-etch polymer 26 generally comprisesthe polymer residue by-products remaining after the etch and photoresiststrip.

[0029] According to the invention, the wet etch cleaning compositioncomprises relative amounts of one or more cleaning agents to selectivelyetch the DARC layer 18 at a desired rate without substantially etchingthe ILD layer 16. The wet etch composition can have a pH over a range ofabout 3.5 to about 14, and is preferably about pH 6.5. The cleaningcomposition preferably comprises tetramethylammonium fluoride (TMAF), amixture of TMAF and hydrogen fluoride (HF), or a mixture of TMAF andtrimethylammonium hydroxide (TMAH).

[0030] In one embodiment, the cleaning composition comprises aneffective amount of tetramethylammonium fluoride (TMAF) to selectivelyremove the DARC layer 18 and post-etch polymer 26 relative to the low kdielectric layer 16. Preferably, the cleaning composition comprisesabout 10 to about 40 wt % TMAF. The TMAF solution can be prepared byknown methods in the art. For example, a TMAF cleaning composition canbe prepared by combining a standard aqueous (49 wt %) HF solution with astandard aqueous (25 wt %) TMAH solution in an effective volume ratioconcentration such that the resultant composition preferably comprisesabout 10 to about 40 wt % TMAF.

[0031] In another embodiment, the cleaning composition can comprise aneffective amount of TMAF combined with an amount of hydrogen fluoride(HF), to selectively remove the DARC layer 18 and post-etch polymermaterial 26. Preferably, the cleaning composition comprises about 10 toabout 40 wt % TMAF and up to about 10 wt % HF. The TMAF/HF cleaningcomposition can be prepared, for example, by combining an aqueous TMAFsolution with about up to about 10 wt % of a standard aqueous (49 wt %)HF solution. In another example, the cleaning composition can also beprepared by combining TMAH (25 wt % solution) with an excess amount ofHF (49 wt % solution) to form a TMAF and HF cleaning composition. Anexample and preferred composition comprises a volume ratio concentrationof TMAH (25 wt %): HF (49 wt %) of about 4:1 to about 11:1, preferablyabout a 9:1 volume ratio.

[0032] In yet another embodiment, the cleaning composition is formulatedwith effective amounts of TMAF and TMAH cleaning agents to selectivelyremove the DARC layer 18 and post-etch polymer material 26. Preferably,the cleaning composition comprises about 10 to about 40 wt % TMAF and upto about 25 wt % TMAH. The TMAF/TMAH cleaning composition can beprepared by combining a standard aqueous (25 wt %) TMAH solution with anaqueous TMAF solution.

[0033] To avoid undesirable modification of the critical dimensions (CD)of the etched features, the cleaning composition comprises amounts ofthe cleaning agents to provide an etch selectivity ratio of the DARClayer to the low k ILD layer (DARC: low k ILD) that is greater than theDARC: TEOS etch rate ratio of the particular DARC material that isutilized, to limit etching of the low k ILD layer, preferably to aboutzero (0) to less than 50 angstroms. The etch rates of various DARCmaterials are shown in Table 1 of the Example. Preferably, the etch rateratio of the DARC: low k ILD layer is greater than 2:1, preferablygreater than 5:1, preferably about 9:1 to about 11:1 or greater, andmore preferably about 100:1 to about 1,000:1 or greater. The cleaningcomposition provides effective and easy removal of the DARC layer 18 andpost-etch polymer 26 while controlling the etch rate of other waferregions such that essentially no etching of the ILD layer 16 occursduring the cleaning step.

[0034] The cleaning composition can be applied to the wafer in variousways. For example, the cleaning composition can be sprayed onto thewafer, or the wafer can be dipped or immersed into a bath of thecleaning composition, among others.

[0035] The cleaning composition can be used at a temperature of about 5to about 65° C., preferably about 20 to about 50° C. The length of thecontact of the cleaning composition with the wafer surface generallydepends on the thickness and the character of the DARC layer. Forexample, a 6-minute dip using a 9:1 volume ratio of TMAH (25 wt %): HF(49 wt %) can be used to remove about 600 angstroms of a DARC film, withthe wet etch rate for the low k ILD layer being about zero (0). Bycomparison, in six (6) minutes, the foregoing composition typicallyremoves about 200 angstroms of a TEOS deposited layer, which causes CDloss of features etched in a TEOS ILD layer. The contact time of thecomposition generally ranges from about 1 to about 15 minutes.

[0036] After the cleaning step, a conductive metal layer 30 can then bedeposited to fill the trench 24 and the contact opening 22, as shown inFIG. 5. Examples of conductive metals include aluminum, copper, andtungsten. The conductive metal 30 can be deposited by conventionalmethods, such as physical vapor deposition (PVD) (sputtering) or CVD.The metal layer 36 can be subsequently planarized by chemical mechanicalplanarization (CMP) or etched back so that the metal remains isolated inpaths within the trench 24 and opening 22, resulting in the metal line(interconnect or contact) 32, conducting plug 34, and metal layer 36, asdepicted in FIG. 6.

[0037] In another embodiment of the method of the invention, a singleopening or via can be etched through the ILD layer, cleaned with thecleaning composition, and filled with a conductive metal to form a viaplug, as depicted in FIGS. 7-10.

[0038] For example, the wafer fragment shown in FIG. 2, having a low kdielectric (ILD) layer 16′, DARC layer 18′, and overlying photoresistlayer 20′, can be patterned and etched to form a single opening or via22′, as illustrated in FIG. 7. Referring to FIG. 8, after the etch stepand a photoresist strip step, a post-etch cleaning (arrows 26′) can thenbe performed using the cleaning composition of the invention toselectively etch the DARC layer 18′ and any post-etch polymer 26′, withlittle or no etching of the low k ILD layer 16′, preferably removingless than 50 angstroms of the ILD layer.

[0039] Thereafter, a conductive metal layer 30′ can be deposited to fillthe opening 22′, as shown in FIG. 9. The metal layer 36′ can besubsequently planarized by CMP or etched back so that the metal remainsisolated in the contact opening 22′, resulting in the conducting plug34′, as shown in FIG. 10.

EXAMPLE

[0040] Wafers were provided with various oxide film layers and DARC filmlayers, as shown in Table 1 below. The wafers were immersed for 6minutes in a bath containing a 9:1 volume ratio TMAH:HF solution (25 wt% TMAH solution; 49 wt % HF solution). The pH of the solution was 6.5,and the bath temperature was 21.5° C. TABLE 1 Thickness Δ¹ Film type(angstroms) Thermal oxide 33 Rich BPSG, annealed 74 TEOS, as deposited223 320 DARC 330 I-line DARC 454 DUV DARC 740 HER DARC >1006 Fuse DARC547 Low k film 0

[0041] All DARC films were stripped and piranhaed before being tested.The low k film was not etched at all during a 15 minute dip.

[0042] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

What is claimed is:
 1. A method of forming a conductive structure,comprising the steps of: providing a wafer comprising a substrate and anoverlying low k dielectric layer; forming a layer of dielectricantireflective coating over the low k dielectric layer; forming aphotoresist layer over the dielectric antireflective coating layer;etching an opening through the low k dielectric layer to an active areaon the substrate; and contacting the wafer with a cleaning solutioncomprising trimethylammonium fluoride to selectively remove thedielectric antireflective coating layer and post-etch polymer material.2. The method of claim 1, wherein the cleaning solution comprises anamount of trimethylammonium fluoride to provide an etch rate ratio ofthe dielectric antireflective coating layer to the low k dielectriclayer greater than the etch rate ratio of the dielectric antireflectivecoating layer to a TEOS layer.
 3. The method of claim 2, wherein theetch rate is greater than 2:1.
 4. The method of claim 2, wherein theetch rate is greater than 5:1.
 5. The method of claim 2, wherein theetch rate is greater than 10:1.
 6. The method of claim 2, wherein thecleaning solution comprises about 10 to about 40 wt % oftrimethylammonium fluoride.
 7. The method of claim 2, wherein thecleaning solution further comprises hydrogen fluoride.
 8. The method ofclaim 7, wherein the cleaning solution comprises about 10 to about 40 wt% of trimethylammonium fluoride and up to about 10 wt % hydrogenfluoride.
 9. The method of claim 2, wherein the cleaning solutionfurther comprises trimethylammonium hydroxide.
 10. The method of claim9, wherein the cleaning solution comprises about 10 to about 40 wt % oftrimethylammonium fluoride and about 0 to about 25-wt %trimethylammonium hydroxide.
 11. The method of claim 1, wherein thecleaning solution has a pH of about 3.5 to about
 14. 12. The method ofclaim 1, wherein the temperature of the cleaning solution is about 5° C.to about 65° C.
 13. The method of claim 1, wherein the temperature ofthe cleaning solution is about 20° C. to about 50° C.
 14. The method ofclaim 1, wherein the contacting step is for a time period effective toremove the dielectric antireflective coating layer and the post-etchpolymer with substantially no etching of the low k dielectric layer. 15.The method of claim 14, wherein the contacting step comprises removingup to about 600 angstroms of the dielectric antireflective coating layerwithin an about six minute time period.
 16. The method of claim 14,wherein the contacting step comprises an about 1 to about 15 minute timeperiod.
 17. The method of claim 14, wherein the contacting step resultsin etching of less than 50 angstroms of the low k dielectric layer. 18.The method of claim 1, wherein the contacting step comprises dipping thewafer in the cleaning solution.
 19. The method of claim 1, wherein thecontacting step comprises spraying the cleaning solution onto the wafer.20. The method of claim 1, further comprising after the contacting step,the step of depositing a conductive material to fill the opening.
 21. Amethod of forming a conductive structure, comprising the steps of:providing a wafer comprising a substrate, an overlying carbon doped lowk dielectric layer, an overlying dielectric antireflective coatinglayer, and an opening formed through said layers to the substrate; andcontacting the wafer with a cleaning solution comprising an amount oftrimethylammonium fluoride to selectively etch the dielectricantireflective coating layer and overlying polymer material.
 22. Themethod of claim 21, wherein the cleaning solution provides an etch rateratio of the dielectric antireflective coating layer to the low kdielectric layer greater than the etch rate ratio of the dielectricantireflective coating layer to a TEOS layer.
 23. The method of claim22, wherein the rate of etching the dielectric antireflective coatinglayer to the rate of etching the low k dielectric layer is a ratiogreater than about 5:1.
 24. The method of claim 22, wherein the rate ofetching the dielectric antireflective coating layer to the rate ofetching the low k dielectric layer is a ratio greater than about 10:1.25. The method of claim 21, wherein the contacting step is for a timeperiod of about 1 to about 15 minutes, and less than 50 angstroms of thedielectric layer is etched.
 26. A method off forming a conductivestructure, comprising the steps of: forming a carbon doped low kdielectric layer over a substrate of a wafer; forming a dielectricantireflective coating layer over the low k dielectric layer; forming aphotoresist layer comprising an organic polymer material over thedielectric antireflective coating layer; etching an opening through thedielectric layer to the substrate; and contacting the wafer with acleaning solution comprising an effective amount of trimethylammoniumfluoride to selectively remove the dielectric antireflective coatinglayer and post-etch polymer.
 27. The method of claim 26, wherein thecleaning solution provides an etch rate ratio of the dielectricantireflective coating layer to the low k dielectric layer of greaterthan 5:1.
 28. The method of claim 26, wherein the cleaning solutionprovides an etch rate ratio of the dielectric antireflective coatinglayer to the low k dielectric layer of greater than 10:1.
 29. The methodof claim 26, wherein the cleaning solution comprises about 10 to about40 wt % of trimethylammonium fluoride.
 30. The method of claim 29,wherein the cleaning solution further comprises up to about 10 wt %hydrogen fluoride.
 31. The method of claim 29, wherein the cleaningsolution further comprises up to about 25 wt % trimethylammoniumhydroxide.
 32. The method of claim 26, wherein the step of forming thecarbon-doped low k dielectric layer comprises depositing acarbon-substituted silane source gas and an oxygen source gas onto thesubstrate.
 33. The method of claim 32, wherein the silane source gascomprises trimethylsilane, and the oxygen source is selected from thegroup consisting of N₂O and O₂.
 34. The method of claim 32, wherein thestep of forming the low k dielectric layer comprises flowing about 60 toabout 1000 sccm of the silane source gas, and about 50 to about 500 sccmof the oxygen source gas over the substrate.
 35. The method of claim 34,wherein the step of forming the low k dielectric layer further comprisesflowing about 200 to about 1000 sccm of helium.
 36. The method of claim26, wherein the step of forming the low k dielectric layer comprisesflowing about 60 to about 1000 sccm trimethylsilane and about 200 toabout 1000 sccm N₂O.
 37. The method of claim 36, wherein the step offorming the low k dielectric layer further comprises flowing about 200to about 1000 sccm of helium.
 38. The method of claim 26, wherein thestep of forming the low k dielectric layer comprises flowing about 500to about 700 sccm trimethylsilane, and about 80 to about 150 sccm O₂.39. The method of claim 26, wherein the step of forming the low kdielectric layer is at a temperature of about 300° C. to about 450° C.40. The method of claim 26, wherein the step of forming the low kdielectric layer comprises plasma enhanced chemical vapor deposition.41. The method of claim 26, wherein the low k dielectric layer has adielectric constant of about 2.5 to about 3.5.
 42. The method of claim26, wherein the step of forming the dielectric antireflective coatinglayer comprises depositing a plasma comprising a silicon source gas andan oxygen source gas.
 43. The method of claim 42, wherein the siliconsource gas comprises silane, and the oxygen source gas comprises N₂O.44. The method of claim 26, wherein the dielectric antireflectivecoating layer comprises silicon-rich oxynitride or a silicon-rich oxide.45. The method of claim 44, wherein the dielectric antireflectivecoating layer comprises a silicon-rich oxynitride having the formulaSi_(x)O_(y)N_(z):H where x is 0.30 to 0.65, y is 0.02 to 0.56, and z is0.05 to 0.33.
 46. The method of claim 44, wherein the dielectricantireflective coating layer comprises a silicon-rich oxide having theformula Si_(x)O_(y):H, where x is 0.30 to 0.65, and y is 0.25 to 0.60.47. The method of claim 26, wherein the step of forming the dielectricantireflective coating layer comprises chemical vapor deposition. 48.The method of claim 26, wherein the step of forming the dielectricantireflective coating layer comprises plasma enhanced chemical vapordeposition.
 49. The method of claim 42, wherein the step of forming thedielectric antireflective coating layer comprises flowing about 40 toabout 300 sccm of a silicon source gas, and about 80 to about 600 sccmof an oxygen source gas.
 50. The method of claim 26, wherein thephotoresist layer comprises a novolac resin.
 51. The method of claim 26,wherein the step of forming the opening comprises a plasma etch process.52. The method of claim 26, wherein the step of etching the openingcomprises a damascene etch process.
 53. The method of claim 52, whereinthe opening comprises a contact opening and a trench.
 54. The method ofclaim 52, wherein the opening comprises a contact opening or via. 55.The method of claim 26, wherein the step of etching the openingcomprises exposing an active area on the substrate.
 56. The method ofclaim 55, wherein the active area comprises a metal line.
 57. The methodof claim 55, wherein the active area comprises a source/drain region.58. A method of forming a dual damascene structure in a semiconductordevice, comprising the steps of: providing a substrate comprising anactive area; forming a low k dielectric layer over the active area;forming a dielectric antireflective coating layer over the low kdielectric layer; forming a photoresist layer over the dielectricantireflective coating layer; etching the insulating layer to form atrench and an opening extending to the active area in the substrate; andselectively removing post-etch polymer and the dielectric antireflectivecoating layer with a cleaning solution comprising trimethylammoniumfluoride in an amount effective to selectively etch the dielectricantireflective coating layer to the low k dielectric layer at an etchrate ratio of greater than 5:1.
 59. The method of claim 58, wherein theetch rate ratio is greater than 10:1.
 60. The method of claim 58,wherein the cleaning solution comprises about 10 to about 40 weight %trimethylammonium fluoride.
 61. The method of claim 60, wherein thecleaning solution further comprises up to about 10 weight % hydrogenfluoride.
 62. The method of claim 60, wherein the cleaning solutionfurther comprises up to about 25 wt % trimethylammonium hydroxide.
 63. Amethod of cleaning a surface, comprising the steps of: providing a wafersubstrate comprising overlying layers of a carbon-doped low k dielectriclayer, and a dielectric antireflective coating layer; and contacting thewafer with a cleaning solution comprising trimethylammonium fluoride toselectively remove the dielectric antireflective coating layer andpolymer material on the wafer.
 64. The method of claim 63, wherein thecleaning solution comprises the trimethylammonium fluoride in an amountto provide an etch rate ratio of the dielectric antireflective coatinglayer and the low k dielectric layer of greater than 5:1.
 65. The methodof claim 63, wherein the cleaning solution comprises thetrimethylammonium fluoride in an amount to provide an etch rate ratio ofthe dielectric antireflective coating layer and the low k dielectriclayer of greater than 10:1.
 66. The method of claim 63, wherein thecleaning solution comprises about 10 to about 40% wt trimethylammoniumfluoride.
 67. The method of claim 66, wherein the cleaning solutionfurther comprises up to about 10 wt % hydrogen fluoride.
 68. The methodof claim 66, wherein the cleaning solution further comprises up to about25 wt % trimethylammonium fluoride.
 69. The method of claim 63, whereinthe dielectric antireflective coating layer comprises silicon-richoxynitride having the formula Si_(x)O_(y)N_(z):H where x is 0.30 to0.65, y is 0.02 to 0.56, and z is 0.05 to 0.33.
 70. The method of claim63, wherein the dielectric antireflective coating layer comprises asilicon-rich oxide having the formula Si_(x)O_(y):H, where x is 0.30 to0.65, and y is 0.25 to 0.60.
 71. The method of claim 63, wherein thewafer further comprises an opening etched into the low k dielectriclayer to the substrate, the opening having a critical dimension.
 72. Themethod of claim 71, wherein the opening has a width dimension less thanabout 0.25 μm, and the step of removing etches less than about 50angstroms of the low k dielectric layer during a contact period with thecleaning solution of up to about 15 minutes.
 73. The method of claim 71,wherein the opening has an aspect ratio greater than about 0.5.
 74. Themethod of claim 63, wherein the contacting step is for a time effectiveto remove the polymer material and the dielectric antireflective coatinglayer, wherein less than about 50 angstroms of the low k dielectriclayer are removed.
 75. A semiconductor processing method, comprising thesteps of: providing a substrate comprising an active area; chemicalvapor depositing a carbon-doped low k dielectric layer over a substrateby flowing about 60 to about 700 sccm of a carbon-substituted silanesource gas, and about 100 to about 1000 sccm of an oxygen source gasover the active area on the substrate; chemical vapor depositing adielectric antireflective coating layer comprising silicon-richoxynitride or silicon-rich oxide over the dielectric layer, forming alayer of photoresist over the dielectric antireflective coating layer;photolithographically patterning the photoresist layer to form apatterned masking layer; etching the low k dielectric layer to form anopening therethrough to the active area on the substrate; and applying acleaning solution comprising trimethylammonium fluoride for a timeeffective to selectively remove the dielectric antireflective coatinglayer and post-etch polymer at an etch rate ratio of the dielectricantireflective coating layer to the low k dielectric layer of greaterthan 5:1.
 76. The method of claim 75, wherein the etch rate ratio of thedielectric antireflective coating layer to the low k dielectric layer ofgreater than 10:1.
 77. The method of claim 75, wherein the low kdielectric layer has a dielectric constant of about 2.5 to about 3.5.78. The method of claim 75, wherein the cleaning solution comprisesabout 10 to about 40 wt % trimethylammonium fluoride.
 79. The method ofclaim 78, wherein the cleaning solution further comprises up to about 10wt % hydrogen fluoride.
 80. The method of claim 78, wherein the cleaningsolution further comprises about 0 to about 25 wt % trimethylammoniumhydroxide.
 81. The method of claim 75, wherein the applying stepcomprises removing up to about 600 angstroms of the dielectricantireflective coating layer and substantially no measurable removal ofthe low k dielectric layer over an about 6 minute time period.
 82. Themethod of claim 75, wherein less than 50 angstroms of the low kdielectric layer is removed.
 83. The method of claim 75, wherein thestep of depositing the low k dielectric layer comprises flowing about 60to about 150 sccm trimethylsilane, and about 300 to about 500 sccm N₂O.84. The method of claim 75, wherein the step of depositing the low kdielectric layer comprises flowing about 500 to about 700 sccmtrimethylsilane, and about 80 to about 150 sccm O₂.
 85. A cleaningcomposition comprising: an aqueous solution comprising one or morecleaning agents in amounts effective to selectively remove a dielectricantireflective coating layer overlying a carbon-doped low k dielectriclayer at an etch rate of the dielectric antireflective coating layer tothe low k dielectric layer that is greater than the etch rate of thedielectric antireflective coating layer to a TEOS layer.
 86. Thecleaning composition of claim 85, wherein the etch rate of thedielectric antireflective coating layer to the low k dielectric layer isgreater than 5:1.
 87. The cleaning composition of claim 85, wherein theetch rate of the dielectric antireflective coating layer to the low kdielectric layer is greater than 10:1.
 88. The cleaning composition ofclaim 85, comprising trimethylammonium fluoride.
 89. The cleaningcomposition of claim 88, comprising about 10 to about 40 wt %trimethylammonium fluoride.
 90. The cleaning composition of claim 89,further comprising up to about 10 wt % hydrogen fluoride.
 91. Thecleaning composition of claim 89, further comprising up to about 25 wt %trimethylammonium hydroxide.
 92. The cleaning composition of claim 88,having a pH of about 3.5 to about
 14. 93. A cleaning composition,comprising: an aqueous solution comprising about 10 to about 40 wt %trimethylammonium fluoride to selectively etch an dielectricantireflective coating layer overlying a low k dielectric layer; thedielectric antireflective coating layer comprising a silicon-richoxynitride or silicon-rich oxide.
 94. The cleaning composition of claim93, further comprising about 0 to about 10 wt % hydrogen fluoride. 95.The cleaning composition of claim 94, comprising the trimethylammoniumfluoride and hydrogen fluoride in amounts such that contact of thecleaning composition with a low k dielectric layer for a time period ofup to about 15 minutes removes less than 50 angstroms of the low kdielectric layer.
 96. The cleaning composition of claim 93, furthercomprising about 0 to about 25 wt % trimethylammonium hydroxide.
 97. Thecleaning composition of claim 96, comprising the trimethylammoniumfluoride and trimethylammonium hydroxide in amounts such that contact ofthe cleaning composition with a low k dielectric layer for a time periodof up to about 15 minutes removes less than 50 angstroms of the low kdielectric layer.
 98. The cleaning composition of claim 93, wherein thelow k dielectric layer comprises a carbon-doped low k dielectricmaterial.
 99. The cleaning composition of claim 98, wherein the low kdielectric layer comprises silicon oxide formed by chemical vapordeposition of a carbon-substituted silane precursor and an oxygen sourcegas.
 100. The cleaning composition of claim 99, wherein the low kdielectric layer is formed by deposition of trimethylsilane and N₂O.101. The cleaning composition of claim 99, wherein the low k dielectriclayer is formed by deposition of trimethylsilane and O₂.
 102. A cleaningcomposition, comprising: an aqueous solution comprising about 10 toabout 40 wt % trimethylammonium fluoride to selectively etch adielectric antireflective coating layer overlying a low k dielectriclayer.
 103. The cleaning composition of claim 102, comprising an amountof trimethylammonium fluoride to effect an etch rate ratio of thedielectric antireflective coating layer: the dielectric layer of greaterthan 5:1.
 104. The cleaning composition of claim 102, comprising anamount of trimethylammonium fluoride to effect an etch rate ratio of thedielectric antireflective coating layer: the low k dielectric layer ofgreater than 10:1.
 105. The cleaning composition of claim 102,comprising an amount of trimethylammonium fluoride to effect an etchrate ratio of the dielectric antireflective coating layer: the low kdielectric layer of greater than 100:1.
 106. The cleaning composition ofclaim 102, comprising amounts of the trimethylammonium fluoride suchthat less than 50 angstroms of the low k dielectric layer is removedafter contact of the cleaning composition for up to about 15 minutes.107. The cleaning composition of claim 102, further comprising 0 toabout 10 wt % hydrogen fluoride.
 108. The cleaning composition of claim102, further comprising 0 to about 25 wt % trimethylammonium hydroxide.109. The cleaning composition of claim 102, wherein the low k dielectriclayer comprises a carbon-doped low k dielectric material.
 110. Thecleaning composition of claim 102, wherein the dielectric antireflectivecoating layer comprises a silicon-rich oxynitride or silicon-rich oxide.111. The cleaning composition of claim 110, wherein the dielectricantireflective coating layer comprises a silicon-rich oxynitride of theformula Si_(x)O_(y)N_(z):H where x is 0.30 to 0.65, y is 0.02 to 0.56,and z is 0.05 to 0.33.
 112. The cleaning composition of claim 110,wherein the dielectric antireflective coating layer comprises asilicon-rich oxide of the formula Si_(x)O_(y):H, where x is 0.30 to0.65, and y is 0.25 to 0.60.